1. Field of the Invention
The invention relates to a high voltage metal-oxide-semiconductor (herein after abbreviated as HV MOS) device and a layout pattern thereof, and more particularly, to a high voltage lateral double-diffused metal-oxide-semiconductor (HV-LDMOS) device and a layout pattern thereof.
2. Description of the Prior Art
Double-diffused MOS (DMOS) transistor devices have drawn much attention in power devices having high voltage capability. The conventional DMOS transistor devices are categorized into vertical double-diffused MOS (VDMOS) transistor device and lateral double-diffused MOS (LDMOS) transistor device. Having advantage of higher operational bandwidth, higher operational efficiency, and convenience to be integrated with other integrated circuit due to its planar structure, LDMOS transistor devices are prevalently used in high operational voltage environment such as CPU power supply, power management system, AC/DC converter, and high-power or high frequency (HF) band power amplifier. The essential feature of LDMOS transistor device is a lateral-diffused drift region with low dope concentration and large area. The drift region is used to alleviate the high voltage between the drain and the source, therefore the LDMOS transistor device can have higher breakdown voltage.
Please refer to FIG. 1, which is a cross-sectional view of a conventional HV-LDMOS transistor device. As shown in FIG. 1, the conventional HV-LDMOS transistor device 10 having a P-type well 20, a source 14 and a P-type heavily doped region 22 formed in the P-type well 20, a gate 16 and a drain 18 is formed on a semiconductor substrate 12. The drain 18 is an N-type heavily doped region formed in an N-type well 30, which is the drift region as mentioned above. The dope concentration and length of the drift region affects the breakdown voltage and the ON-resistance (RON) of the HV-LDMOS transistor device 10. The gate 16 of the HV-LDMOS transistor device 10 is positioned on a gate dielectric layer 40 and extended to cover a portion of a field oxide layer 42.
It is well-known that characteristics of low RON and high breakdown voltage are always required to the HV MOS transistor device. However, breakdown voltage and RON are conflicting parameters with a trade-off relationship. Therefore, a HV LDMOS transistor device that is able to realize high breakdown voltage and low RON is still in need.